Stratix® 10 SoC FPGA Hardware and HPS Overview - 30 Minutes In this training you will learn about the architecture of the Stratix® 10 SoC and FPGA variants. The training provides a description of the variants for Stratix 10 FPGA and an overview of Hyperflex® Architecture and different tiles. You will learn about the Hard Processor System (HPS) and its contents. We begin by discussing the Arm Cortex-A53. The Cache Coherency Unit (CCU) and System MMU (SMMU) memory management blocks are explained next. The bridges between the HPS, FPGA, and SDRAM are also discussed. Finally, the training will give an overview of the boot flow of the device, which will include an explanation of the role the Secure Device Manager (SDM) plays. Course Objectives At course completion, you will be able to: Differentiate the tiles and variants of the Stratix® 10 FPGAs, as well as applications of each device Understand the architecture of the Stratix 10 SoC FPGAs HPS Understand the CCU and SMMU memory management blocks Skills Required Understanding of FPGAs and SoCs desired Embedded software and tools If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OS10SOCHW. FPGA_OS10SOCHW. <p>Stratix 10 SoC FPGA Hardware and HPS Overview</p>