Quartus II Compilation Warnings for Nios II Stratix II 2S60 ROHS Example - Quartus II Compilation Warnings for Nios II Stratix II 2S60 ROHS Example Description You might see the following warnings if you try to compile the Nios II Stratix ® II 2S60 ROHS example design, installed at <Nios II EDS install path> /examples/vhdl/niosII_stratixII_2s60/standard or downloaded from the FPGA Wiki Warning (10541): VHDL Signal Declaration warning at NiosII_stratixII_2s60_standard.vhd(59): used implicit default value for signal "cpu_data_master_read_data_valid_NiosII_stratixII_2s60_standard_clock_0_in" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. Warning (10542): VHDL Variable Declaration warning at altera_europa_support_lib.vhd(340): used initial value expression for variable "arg_copy" because variable was never assigned a value Warning (10542): VHDL Variable Declaration warning at altera_europa_support_lib.vhd(344): used initial value expression for variable "arg_length" because variable was never assigned a value You can safely ignore these warnings. The Nios II Stratix II 2S60 ROHS example is deprecated. Resolution None. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 10.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']