Why doesn't the HDMI FPGA Sink IP assert the SCDC CED_Update register flag when a character error is detected in the HDMI Sink data channel? - Why doesn't the HDMI FPGA Sink IP assert the SCDC CED_Update register flag when a character error is detected in the HDMI Sink data channel? Description Due to a problem in the Quartus® Prime Pro Edition Software v21.2 and earlier, the HDMI FPGA Sink IP core does not assert the SCDC CED_Update register flag when a character error is detected in the high definition media interface (HDMI) sink intellectual property (IP) data channel. This causes the HDMI source IP to read back an incorrect status update from the HDMI sink IP. Resolution This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Errata 1506999619 True ['HDMI'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 21.2 ['Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']