When using Partial Reconfiguration are the PR_DONE, PR_READY, PR_ERROR, and PR_REQUEST pins powered by VCCPGM or VCCIO? - When using Partial Reconfiguration are the PR_DONE, PR_READY, PR_ERROR, and PR_REQUEST pins powered by VCCPGM or VCCIO? Description When using Partial Reconfiguration (PR) the PR_DONE, PR_READY, PR_ERROR, and PR_REQUEST pins will be powered by VCCIO as PR operates in usermode with the device still running while the PR region is being frozen. Related Articles Are the Partial Reconfiguration output pins on Stratix V, Arria V and Cyclone V devices configured as Open Drain by default, when these pins are enabled in my Quartus II project? Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']