Why is the output clock signal of the ALTCLKCTRL Intel® FPGA IP stucked high in Intel® Arria® 10 SX devices? - Why is the output clock signal of the ALTCLKCTRL Intel® FPGA IP stucked high in Intel® Arria® 10 SX devices? Description Due to a problem in the Intel® Quartus® Prime Software, you might see that for Intel® Arria® 10 SX devices, the ALTCLKCTRL Intel® FPGA IP output clock signal is stucked high when it's assigned to the CLKCTRL_2L_G_I17 location. Resolution To work around this problem, create a dummy instance of the ALTCLKCTRL Intel® FPGA IP, and add the following assignments in the Quartus settings file ( .qsf ) to preserve the dummy instance and to fix the location to CLKCTRL_2L_G_I17 . set_location_assignment CLKCTRL_2L_G_I17 -to <dummy_clkctrl_instance_name> set_instance_assignment -name PRESERVE_FANOUT_FREE_WYSIWYG ON -to <dummy_clkctrl_instance_name> Custom Fields values: ['novalue'] Troubleshooting 2206125411 False ['ALTCLKCTRL IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 18.1 ['Arria® 10 SX FPGA'] ['novalue'] ['novalue'] ['novalue']