Wildcard LLR Assignments Result in PR Boundary Ports Not Constrained to the LLR - Wildcard LLR Assignments Result in PR Boundary Ports Not Constrained to the LLR Description When you compile a design that uses wildcards in the LogicLock region (LLR) assignments, the wildcards are not obeyed and the partial reconfiguration boundary ports are not constrained to the LLR. For example, the following LLR assignment is not obeyed: auto|dir[*]~IPORT Resolution To avoid this issue, you must manually expand each wildcard, and create individual assignments for each node. For example, expand the previous example LLR assignment as follows: auto|dir[0]~IPORT auto|dir[1]~IPORT Custom Fields values: ['novalue'] Troubleshooting FB413121; True ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 17.0 16.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']