Constraining Double Data Rate Source Synchronous Interfaces - Same Course in Japanese: ダブル・データ・レートのソース同期インタフェースに対する制約 Same Course in Simplified Chinese: 约束双倍数据速率源同步接口 29 Minutes This training provides an introduction to double data rate interfaces and some of the challenges involved in constraining them. You’ll learn about clock constraints, data constraints, and timing exceptions for both input and output DDR interfaces. Finally, you’ll learn how to analyze DDR source synchronous interface timing with the TimeQuest timing analyzer. This course uses the Quartus® II software v13.0. Course Objectives At course completion, you will be able to: Constrain double data rate source synchronous interfaces with SDC constraints Analyze timing for double data rate source synchronous interfaces with the TimeQuest timing Analyzer Skills Required Knowledge of static timing analysis concepts Knowledge of source synchronous interface theory Completion of “Constraining source synchronous Interfaces” online training If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_ODDR1000. FPGA_ODDR1000. <p>Constraining Double Data Rate Source Synchronous Interfaces</p>