Is it possible to perform boundary scan testing over the Hard Processor System (HPS) JTAG pins? - Is it possible to perform boundary scan testing over the Hard Processor System (HPS) JTAG pins? Description No, it is not possible to perform boundary scan testing over the HPS JTAG pins. However tbe HPS I/O pins do support boundary scan testing through the JTAG pins of the FPGA. The BSDL files generated via the Quartus® II software for Cyclone® V SoC devices will include HPS I/O pins that support boundary scan. Note: For Cyclone V SoC FPGAs you must power up both the HPS and FPGA to perform a boundary scan test (BST). Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']