JPEG-LS-D: Lossless & Near-Lossless JPEG-LS Decoder - The JPEG-LS-D core, a highly efficient & low-power, lossless & near-lossless image decompression engine & compliant to the JPEG-LS, ISO/IEC 14495-1 standard, can decompress any JPEG-LS stream or JPEG… CAST develops, sells, and supports digital Silicon IP Cores which electronic system designers use to shorten development time and lower production risk. CAST uniquely gives system designers the CAST… Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST FPGA Arria® V SX FPGA Cyclone® IV E FPGA Cyclone® IV GX FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE FPGA Cyclone® V ST FPGA Cyclone® V SX FPGA Agilex™ 3 FPGA C-Series Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Cyclone® 10 GX FPGA Cyclone® 10 LP FPGA MAX® 10 FPGA Stratix® 10 AX FPGA Stratix® 10 DX FPGA Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA Stratix® III FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA The JPEG-LS-D core implements a highly efficient and low-power, lossless and near-lossless image decompression engine that is compliant to the JPEG-LS, ISO/IEC 14495-1 standard. The decoder core can decompress any JPEG-LS stream or JPEG-LS payload of image container formats, such as DICOM (Digital Imaging and Communications in Medicine). It accepts compressed streams of images with up to 16-bit per color samples and up to four color components, in all widely used color subsampling formats. Supporting oversize image dimension parameters, the core can decode images with resolutions exceeding 64k x 64k pixels. The easy-to-use JPEG-LS-D core operates on a standalone basis, parsing marker segments and decompressing coded data with no assistance from a host processor. The decoder reports the image format (i.e., resolution, subsampling format, and color sample depth) to the system, so that the decoded images are properly further processed and/or displayed. Application (APP) or comment (COM) marker segments—which are typically used to embed metadata in the compressed stream—are also passed to the system via a dedicated interface. SoC integration is straightforward thanks to standardized AMBA® interfaces. The core accepts compressed data and outputs pixel data, frame format information, and APP or COM marker segments via AXI4-Stream interfaces, and it provides access to its control and status registers via a 32-bit APB interface. A wrapper that bridges the AXI-Stream interfaces to AXI4 can optionally be delivered with the core. The core is designed with industry best practices, and its reliability has been proven through both rigorous verification and silicon validation. The deliverables include a complete verification environment and a bit-accurate software model. Video and Image Processing Access Aerospace Broadcast Consumer Data Center Cloud (Public, Private, Hybrid) Data Center OEM (IHV, ISV, SI, VAR) Defense Industrial Medical Test Transportation Wireless JPEG-LS-D: Lossless & Near-Lossless JPEG-LS Decoder Key Features JPEG-LS ISO/IEC 14495-1 support, w/ all encoding parameters (optional near lossless). More than 64Kx64K, up to 16 bits/color sample & up to 4 colors. Offering Brief Yes Yes No Yes Encrypted VHDL Verilog Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST FPGA Arria® V SX FPGA Cyclone® IV E FPGA Cyclone® IV GX FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE FPGA Cyclone® V ST FPGA Cyclone® V SX FPGA Agilex™ 3 FPGA C-Series Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Cyclone® 10 GX FPGA Cyclone® 10 LP FPGA MAX® 10 FPGA Stratix® 10 AX FPGA Stratix® 10 DX FPGA Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA Stratix® III FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Yes Yes 24.3.1 Offering Brief Production a1JUi0000049U6pMAE What's Included Verilog/System Verilog, Encrypted Verilog/System Verilog, or FPGA netlist Ordering Information JPEG-LS-D a1JUi0000049U6pMAE Production Intellectual Property (IP) a1MUi00000BO8rRMAT a1MUi00000BO8rRMAT Member 2026-04-21T12:58:28.000+0000 The JPEG-LS-D core, a highly efficient & low-power, lossless & near-lossless image decompression engine & compliant to the JPEG-LS, ISO/IEC 14495-1 standard, can decompress any JPEG-LS stream or JPEG-LS payload of image container formats. It accepts compressed streams of images with up to 16-bit per color samples & up to 4 color components, in all widely used color subsampling formats, supporting oversize image dimension parameters & resolutions higher than 64k x 64k. With standalone operation, parsing marker segments & decompressing coded data, the core reports back the image format. APP or COM marker segments are also passed to the system via a dedicated interface. Straightforard integration, standardized AMBA® I/F (compressed data & outputs pixel data, frame format information, APP or COM marker via AXI4-Stream - access to control & status registers via 32-bit APB). A wrapper that bridges the AXI-Stream interfaces to AXI4 can optionally be delivered with the core. Partner Solutions