Why does compilation fail during the Support Logic Generation stage when TX & RX simplex transceivers running at different data rates are placed on the same channel? - Why does compilation fail during the Support Logic Generation stage when TX & RX simplex transceivers running at different data rates are placed on the same channel? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.1 and earlier, when TX and RX simplex transceivers running at different data rate are placed on the same channel, the compilation will fail at the Support-Logic Generation stage during compilation with the following error message: Error(21842): Support logic cannot be generated because IP components used in the design have conflicting settings Error(21843): Conflict 0 ---------------------------------------------------------------- Error(21843): Input variables: Error(21843): user.bb_f_ux_tx[0] -> du_inst|sdi_mr_du_sys_inst|tx_phy|tx_phy|dphy_hip_inst|persystem[0].perxcvr[0].fgt.tx_ux.x_bb_f_ux_tx Error(21843): flux_mode == FLUX_MODE_CPRI Error(21843): is_used == TRUE Error(21843): location == UX0 Error(21843): user.bb_f_ux_rx[0] -> du_inst|sdi_mr_du_sys_inst|rx_phy|rx_phy|dphy_hip_inst|persystem[0].perxcvr[0].fgt.rx_ux.x_bb_f_ux_rx Error(21843): flux_mode == FLUX_MODE_BYPASS Error(21843): is_used == TRUE Error(21843): location == UX0 Resolution To work around this problem, set the FLUX_MODE to BB_DONT_CARE on the TX side in the Intel® Quartus® Settings File (QSF) using the following setting: set_instance_assignment -name HSSI_PARAMETER "flux_mode=__BB_DONT_CARE__" -to <tx_serial_pin> This problem has been fixed starting with the Intel® Quartus® Prime Pro Edition Software version 22.2. Custom Fields values: ['novalue'] Troubleshooting 15010692479 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.2 21.4 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']