Why does the reset synchronizer chains are treated as length 1 chains? - Why does the reset synchronizer chains are treated as length 1 chains? Description Due to a problem in the Intel® Quartus® Prime Pro Edition software version 20.1, if the head register of a reset synchronizer chain has the assignment SYNCHRONIZER_IDENTIFICATION=FORCED, it will be treated as a chain of length 1 rather than as its intended length. This behavior occurs because the chain is treated as a data synchronizer chain instead of a reset synchronizer chain and it excludes registers with asynchronous reset. Resolution To work around this problem, for any affected reset synchronizer chain, add the SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS assignment on the head register in the Intel® Quartus® Prime Settings File ( .qsf ): set_instance_assignment -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS -to <affected_registers> This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 20.3 Custom Fields values: ['novalue'] Troubleshooting 14011850051 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.3 20.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']