CPRI IP Core Dynamic Clock Switching Does Not Work Correctly - CPRI IP Core Dynamic Clock Switching Does Not Work Correctly Description CPRI IP core variations that target an Arria V, Cyclone V, or Stratix V device should support dynamic clock mode switching from master clocking mode to slave clocking mode, and from slave clocking mode to master clocking mode. However, this feature is not working correctly. Resolution This issue has no workaround. You must set the desired, static clocking mode at configuration time in the CPRI parameter editor with the Operation mode parameter. This issue is fixed in version 14.0 of the CPRI MegaCore function. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 14.0 13.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']