Why can’t I reset the Hard Processor System (HPS) of Intel Agilex® 7 FPGA or Intel® Stratix® 10 FPGA using the Mailbox Client Intel® FPGA IP? - Why can’t I reset the Hard Processor System (HPS) of Intel Agilex® 7 FPGA or Intel® Stratix® 10 FPGA using the Mailbox Client Intel® FPGA IP? Description You might see the Hard Processor System (HPS) on Intel Agilex® 7 SoC FPGA and Intel® Stratix® 10 SoC FPGA fail to reset when issuing the REBOOT_HPS command (0x47) through the Mailbox Client Intel® FPGA IP. The REBOOT_HPS command is not supported by the FPGA core to Secure Device Manager (SDM) interface, trying to reset the HPS from the FPGA core will be unsuccessful. Resolution To work around this problem, you must issue the command to reset the HPS through the JTAG interface using the System Console packet service as described in the AN 936: Executing SDM Commands via JTAG Interface . Extract the contents of the sdm-commands.zip. Open System Console from the Intel® Quartus® Prime Pro Edition Software by clicking Tools -> System Debugging Tools -> System Console. In the terminal window of System Console, change directories to where the file sdm_command.tcl was extracted. Enter the following command: % source sdm_command.tcl Execute the REBOOT_HPS command (0x47) with the exec_command procedure: % exec_command 0x47 The Intel Agilex 7 Hard Processor Technical Reference Manual and Intel Stratix 10 Hard Processor System Technical Reference Manual are scheduled to be updated with the above information. Custom Fields values: ['novalue'] Troubleshooting 15010875618; 18021071848; 14016140607 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 21.1 ['Agilex™ 7 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']