Why are rx_st_sop, rx_st_eop, tx_st_sop and tx_st_eop only a single bit wide when Enable multiple packets per cycle was set when configurating the Intel® Arria® 10 FPGA Avalon® Streaming Interface for PCIe Hard IP in 3.0 x8 mode? - Why are rx_st_sop, rx_st_eop, tx_st_sop and tx_st_eop only a single bit wide when Enable multiple packets per cycle was set when configurating the Intel® Arria® 10 FPGA Avalon® Streaming Interface for PCIe Hard IP in 3.0 x8 mode? Description Due to an issue in the Quartus® II software versions 14.1.1 and earlier, the RTL wrapper file for the 3.0 x8 Intel® Arria® 10 FPGA Hard IP for PCI Express incorrectly maps only a single bit of the lower level two bit wide rx_st_sop , rx_st_eop , tx_st_sop and tx_st_eop signals when Enable multiple packets per cycle is set. Resolution To work around this problem, modify the RTL wrapper file, <variation name>.v or <variation name>.vhd , to export both signal bits. Related Articles When using the Arria V GZ and Stratix V Hard IP for PCI Express in multiple packets per cycle mode, why are the signals rx_st_bardec2 and rx_st_bar2 not created? Custom Fields values: ['novalue'] Troubleshooting 2205848616 False ['PCI Express'] ['FPGA Dev Tools Quartus II Software'] No plan to fix 14.0a10 ['Arria® 10 GX FPGA'] ['novalue'] ['novalue'] ['novalue']