Why does the GTS HDMI IP Design Example fail to compile in Dual Simplex mode? - Why does the GTS HDMI IP Design Example fail to compile in Dual Simplex mode? Description Due to an issue in Quartus® Prime Pro Edition Software version 25.1, the GTS HDMI IP Design operating in Dual Simplex mode on Agilex® 5 FPGA devices fails during the Analysis and Synthesis stage. This error occurs when an HDMI TX instance with a width of 4 is used together with an HDMI RX instance with a width of 3. Error(16045): Instance "my_ds_inst_1|my_hdmi_tx_inst0__hdmi_gts_0__u_hdmi_tx|u_tx_core_phy_intf|reset_sync_txclk" instantiates undefined entity "bitec_hdmi20_reset_sync" Error(16045): Instance "my_ds_inst_1|my_hdmi_rx_inst0__hdmi_gts_0__u_hdmi_rx|u_rx_core_phy_intf|reset_sync_lsclk" instantiates undefined entity "bitec_hdmi20_reset_sync" Error(16045): Instance "my_ds_inst_1|my_hdmi_rx_inst0__hdmi_gts_0__u_hdmi_rx|u_rx_core_phy_intf|rxclk_sync_gen[2].reset_sync_rxclk" instantiates undefined entity "bitec_hdmi20_reset_sync" Error(16045): Instance "my_ds_inst_1|my_hdmi_rx_inst0__hdmi_gts_0__u_hdmi_rx|u_rx_core_phy_intf|rxclk_sync_gen[0].reset_sync_rxclk" instantiates undefined entity "bitec_hdmi20_reset_sync" Error(16045): Instance "my_ds_inst_1|my_hdmi_rx_inst0__hdmi_gts_0__u_hdmi_rx|u_rx_core_phy_intf|rxclk_sync_gen[1].reset_sync_rxclk" instantiates undefined entity "bitec_hdmi20_reset_sync" Error(16045): Instance "my_ds_inst_1|my_hdmi_rx_inst0__hdmi_gts_0__u_hdmi_rx|scdc_i2c_gen.u_i2cslave_scdc|reset_sync_i2c_clk" instantiates undefined entity "bitec_hdmi20_reset_sync" Error(16045): Instance "my_ds_inst_1|my_hdmi_rx_inst0__hdmi_gts_0__u_hdmi_rx|u_hpd_hdlg|reset_sync" instantiates undefined entity "bitec_hdmi20_reset_sync" Error(16045): Instance "my_ds_inst_1|my_hdmi_tx_inst0__hdmi_gts_0__u_hdmi_tx|u_tx_core_phy_intf|TX_XCVR_CLK_SYNC[3].u_clock_sync" instantiates undefined entity "intel_hdmi_clock_sync" Error(16045): Instance "my_ds_inst_1|my_hdmi_tx_inst0__hdmi_gts_0__u_hdmi_tx|u_tx_core_phy_intf|TX_XCVR_CLK_SYNC[2].u_clock_sync" instantiates undefined entity "intel_hdmi_clock_sync" Error(16045): Instance "my_ds_inst_1|my_hdmi_tx_inst0__hdmi_gts_0__u_hdmi_tx|u_tx_core_phy_intf|TX_XCVR_CLK_SYNC[1].u_clock_sync" instantiates undefined entity "intel_hdmi_clock_sync" Error(16045): Instance "my_ds_inst_1|my_hdmi_tx_inst0__hdmi_gts_0__u_hdmi_tx|u_tx_core_phy_intf|TX_XCVR_CLK_SYNC[0].u_clock_sync" instantiates undefined entity "intel_hdmi_clock_sync" Error(16045): Instance "my_ds_inst_1|my_hdmi_rx_inst0__hdmi_gts_0__u_hdmi_rx|u_rx_core_phy_intf|rx_xcvr_clk_sync[2].u_clock_sync" instantiates undefined entity "intel_hdmi_clock_sync" Error(16045): Instance "my_ds_inst_1|my_hdmi_rx_inst0__hdmi_gts_0__u_hdmi_rx|u_rx_core_phy_intf|rx_xcvr_clk_sync[1].u_clock_sync" instantiates undefined entity "intel_hdmi_clock_sync" Error(16045): Instance "my_ds_inst_1|my_hdmi_rx_inst0__hdmi_gts_0__u_hdmi_rx|u_rx_core_phy_intf|rx_xcvr_clk_sync[0].u_clock_sync" instantiates undefined entity "intel_hdmi_clock_sync" Resolution This problem is fixed beginning with version 25.1.1 of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting QS-36706 novalue ['Interfaces Audio/Video HDMI (Primary)'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 25.1.1 25.1 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']