Why does compilation fail in the Fitter stage for designs that contain the Multi Channel DMA Intel® FPGA IP for PCI Express? - Why does compilation fail in the Fitter stage for designs that contain the Multi Channel DMA Intel® FPGA IP for PCI Express? Description Designs that contain the Multi Channel DMA Intel® FPGA IP for PCI Express will fail in the Fitter stage of compilation if the Enable PIPE PHY Interface option is not checked in the MCDMA Settings tab of the IP parameter editor. Resolution Ensure the Enable PIPE PHY Interface option is selected in the MCDMA Settings tab of the Multi Channel DMA Intel® FPGA IP for PCI Express parameter editor. This problem is scheduled to be resolved in a future release of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 14015243427 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.4 21.2 ['Agilex™ 7 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']