Why do the TX CLK and RX CLK show unexpected values in the F‑Tile Ethernet Toolkit? - Why do the TX CLK and RX CLK show unexpected values in the F‑Tile Ethernet Toolkit? Description The TX_CLK and RX_CLK frequencies are measured using the reconfig_clk in the F‑Tile Ethernet Hard IP. By default, the reconfig_clk runs at 100 MHz. If the user supplies a different reconfig_clk frequency, the values displayed in the Ethernet Toolkit will be inaccurate. Resolution User can calculate the real frequency from the displayed value: Real clock frequency = frequency value in ETK * frequency of reconfig_clk / 100MHz Custom Fields values: ['novalue'] Troubleshooting QS-51521 novalue ['Interfaces Ethernet F-Tile Ethernet Hard IP (Primary)'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 25.3 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']