Why does the Stratix® 10 PCIe* IP core infer a latch when used in root port mode? - Why does the Stratix® 10 PCIe* IP core infer a latch when used in root port mode? Description When using the Stratix® 10 PCIe* IP core in root port mode, the following inferred latch warning will be reported during analysis and synthesis: Warning (13228): Verilog HDL or VHDL warning at altera_pcie_s10_rp_reg.sv(368): latch inferred for net eop_cycles[3] This problem has been confirmed as a bug. Resolution No workaround for this problem exists. This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 18.1 Custom Fields values: ['novalue'] Troubleshooting 2205676233 False ['Avalon-MM Stratix® 10 Hard IP for PCI Express', 'Avalon-ST Stratix® 10 Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.1 17.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']