Why does the Quartus® Logic Generation Tool report the TX Equalizer settings as 'Ignored' when creating a Tx-only example design for F-Tile JESD204C IP? - Why does the Quartus® Logic Generation Tool report the TX Equalizer settings as 'Ignored' when creating a Tx-only example design for F-Tile JESD204C IP? Description Due to a problem in the Quartus® Prime Pro Edition software version 23.4, you may observe the Quartus Logic Generation Tool incorrectly reports the TX Equalizer settings as 'Ignored' when creating a TX-only example design for F-Tile JESD204C IP. Resolution To work around this problem, you can manually configure the analog parameter instances in the .qsf file. set_instance_assignment -name HSSI_PARAMETER "txeq_main_tap=<parameters value>” -to tx_serial_data[*] set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_1=< parameters value >" -to tx_serial_data[*] set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_2=< parameters value >" -to tx_serial_data[*] set_instance_assignment -name HSSI_PARAMETER "txeq_post_tap_1=< parameters value >" -to tx_serial_data[*] set_instance_assignment -name HSSI_PARAMETER "txeq_main_tap=< parameters value >" -to "tx_serial_data_n[*]" set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_1=< parameters value >" -to "tx_serial_data_n[*]" set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_2=< parameters value >" -to "tx_serial_data_n[*]" set_instance_assignment -name HSSI_PARAMETER "txeq_post_tap_1=< parameters value >" -to "tx_serial_data_n[*]" This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 24.3.1. Custom Fields values: ['novalue'] Troubleshooting 16025868609 novalue ['Interfaces JESD204C (Primary)'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.4 24.3.1 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']