Why isn't a read-valid signal asserted and an error response returned when reading reserved register space? Whereas a valid signal and error response are returned when writing to the reserved register space? - Why isn't a read-valid signal asserted and an error response returned when reading reserved register space? Whereas a valid signal and error response are returned when writing to the reserved register space? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 23.3, you may see a read valid signal is not asserted and an error response is returned when reading reserved register space. In contrast, a valid signal and error response are returned when writing to reserved register space. It's important to note that it operates in a non-functional state, and users will not encounter disruptions. This is ensured by a timeout mechanism, which triggers the return of some dummy response after the timeout. Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition software version 23.4. Custom Fields values: ['novalue'] Troubleshooting 16021979165, 16021744241 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.4 23.3 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']