How do I enable SKP Ordered Set Detection logic in the Intel® Arria® 10 Hard IP core for PCI Express? - How do I enable SKP Ordered Set Detection logic in the Intel® Arria® 10 Hard IP core for PCI Express? Description Beginning with the Intel® Quartus® Prime Software v15.1.2, you can enable SKP Ordered Set detection logic in the Intel® Arria® 10 Hard IP for PCI Express. Resolution To enable the SKP Ordered Set detection logic, follow these steps: Open the IP GUI. Right click on the Intel® Arria® 10 Hard IP for PCI Express banner and select Show Hidden Parameters . Scroll down until you see the enable_skp_det parameter and enter "1". Do not modify any other hidden parameters. Select Generate HDL. The SKP detection logic file skp_det_g3.v will be included in your Intel® Quartus® Prime Software file list for compilation. You can monitor the skp_os signal from the IP core top-level interface. skp_os will assert any time scrambled data exactly matches a SKP pattern when in Gen3 speed. Erroneous Skip Ordered Sets will cause the IP core to enter the recovery state. Other possible causes for entering recovery are, a high bit error rate (BER) or excessive reference clock parts per million (ppm) difference. For additional details on the SKP Ordered Set issue, see " Why does the Intel® Hard IP for PCI Express* in Gen3 configurations, periodically transition from the L0 LTSSM state to the Recovery state then back again? ". Related Articles *** Fatal Error: Segment Violation at (nil) Why does the Intel® Hard IP for PCI Express* in Gen3 configurations, periodically transition from the L0 LTSSM state to the Recovery state then back again? What should I do with the skp_os output on the PCIe Hard IP in Quartus 16.0? Custom Fields values: ['novalue'] Troubleshooting 1506813470 False ['Arria® 10 Cyclone® 10 Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 15.1.2 15.1.2 ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']