Why does the Intel® Arria®10 Low Latency 10G MAC 1G/2.5G/10G (preset) Example Design show timing failure? - Why does the Intel® Arria®10 Low Latency 10G MAC 1G/2.5G/10G (preset) Example Design show timing failure? Description Due to an optimization problem, when using the 1G/2.5G/10G Arria® 10 Low Latency Ethernet MAC Example Design, setup timing failures may be seen between the soft PCS to 10G hard PCS transfer. Resolution To work around this setup timing failure, under-constrain the hold time of the transfer from soft PCS to 8G hard PCS to ease setup timing closure using the constraint below: if {![string equal "quartus_sta" $::TimeQuestInfo(nameofexecutable)] } { set_min_delay -from [get_keepers *|alt_mge16_phy_xcvr_term:*|tx_parallel_data_a10*] -to [get_keepers *|twentynm_pcs*:*|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~tx_clk2_by2_1.reg] -0.2ns } This problem is not scheduled to be fixed in a future version of the Intel® Quartus® Prime Edition Software. Custom Fields values: ['novalue'] Troubleshooting FB: 491624; True ['Low Latency Ethernet 10G MAC IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 17.1 ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']