Why is there a mismatch in PLL location between the Cyclone® V Device Handbook and Intel® Quartus® Prime Software compilation report for Cyclone® V GX C3 devices? - Why is there a mismatch in PLL location between the Cyclone® V Device Handbook and Intel® Quartus® Prime Software compilation report for Cyclone® V GX C3 devices? Description There is a mismatch between the Cyclone® V Device Handbook and Intel® Quartus® Prime Software compilation report for Cyclone® V GX C3 devices. The PLL locations which are reported from the Intel® Quartus® Prime software compilation report are correct and are given below. FRACTIONALPLL_X0_Y14 FRACTIONALPLL_X0_Y32 FRACTIONALPLL_X48_Y1 FRACTIONALPLL_X48_Y32 Resolution The above corrected PLL location is updated in Cyclone® V Device Handbook. Custom Fields values: ['novalue'] Troubleshooting FB: 609493; False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.1 18.0 ['Cyclone® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']