Why does a design with a TX and RX Soft-CDR LVDS SERDES assigned to the same bank in an Intel® Arria® 10 device fail to fit? - Why does a design with a TX and RX Soft-CDR LVDS SERDES assigned to the same bank in an Intel® Arria® 10 device fail to fit? Description Due to a bug in the Quartus® II software, a design that has LVDS SERDES IP core configured in TX mode and RX Soft-CDR mode assigned to the same I/O bank in an Intel® Arria® 10 device will fail at the fitter stage. This is because the phase-locked loop (PLL) instances within the two IP cores will not be correctly merged by the Quartus® II software. Therefore different PLLs will be required for the different LVDS SERDES IP cores. Each I/O bank has only one I/O PLL though. This problem only affects the RX Soft-CDR configuration. RX Non-DPA or RX DPA-FIFO configurations are not affected. Note that the Triple Speed Ethernet IP core uses LVDS SERDES IP configured in RX Soft-CDR mode. Resolution Download the following patch for version 14.0 Intel Arria 10 FPGA Edition of the Quartus® II software: Version 14.0a10 patch 0.01a for Windows (.exe) Version 14.0a10 patch 0.01a for Linux (.run) Version 14.0a10 patch 0.01a readme file (.txt) This problem is fixed starting with the Quartus® II software version 14.1. Custom Fields values: ['novalue'] Troubleshooting 1408040177 False ['LVDS SERDES IP'] ['FPGA Dev Tools Quartus II Software'] 14.1 13.1a10 ['Arria® 10 GT FPGA', 'Arria® 10 GX FPGA', 'Arria® 10 SX FPGA'] ['novalue'] ['novalue'] ['novalue']