Wrong Decoding of MISC1 in DisplayPort Receiver - Wrong Decoding of MISC1 in DisplayPort Receiver Description When used in lane 1 configurations, the DisplayPort IP core receiver may produce wrong MISC1 data as part of the received MSA. The logical state of the 3D video qualifier may also be wrong. This issue is fixed in version 14.1 of the DisplayPort IP core. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 14.1 14.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']