Why do the Intel® MAX® 10 FPGA pin numbers K22 and K21 on the Intel® MAX® 10 FPGA 10M50 Evaluation Kit not support the LVDS IO standard? - Why do the Intel® MAX® 10 FPGA pin numbers K22 and K21 on the Intel® MAX® 10 FPGA 10M50 Evaluation Kit not support the LVDS IO standard?
Description Due to a known problem with the MAX 10® FPGA 10M50 Evaluation Kit , it is incorrectly stated that the Intel® MAX® 10 FPGA pin numbers K22 and K21 can be used as differential clock inputs. However, these pins cannot be used as differential clock inputs. Resolution This information will be corrected in a future version of the Intel® MAX® 10 FPGA 10M50 Evaluation Kit User Guide.
Custom Fields values:
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Troubleshooting
14011069499
False
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['FPGA Dev Tools Quartus® Prime Software Pro']
20.1
16.0
['MAX® 10 10 FPGAs']
['novalue']
['novalue']
['novalue'] - 2023-01-20
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