On-Chip Debugging of Memory Interfaces IP in Altera® FPGA Devices - Same Course in Japanese: Generation 10デバイスにおけるメモリ・インタフェースIPのオンチップ・デバッグ Same Course in Simplified Chinese: 第10代器件内存接口IP的片内调试 30 Minutes This training is part 4 of 4. Altera® Stratix® 10, Arria® 10, and Cyclone® 10 devices introduce a brand new, higher performance architecture for implementing external memory interfaces, including DDR4 running at up to 2.666 Gbps on some devices. This part of the training discusses the use of the EMIF Debug Toolkit and the On-Chip Debug Port. As on previous device families, these tools provide runtime information through a JTAG connection or through software control on the calibration and available margin in a memory interface. Due to the changes in the memory architecture from previous devices, this training also discusses the system design changes required to use these tools with designs that include multiple memory interfaces. Course Objectives At course completion, you will be able to: perform on-Chip debugging of a memory interface using the EMIF Toolkit or the on-Chip debug Toolkit Configure a design with multiple memory interfaces to work with these tools Skills Required Background in digital logic design Basic knowledge of memory interfaces Familiarity with the Altera® Quartus® Prime software Familiarity with memory interfaces in Altera® FPGA devices from the listed prerequisite training classes If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OMEM1124. FPGA_OMEM1124. <p>On-Chip Debugging of Memory Interfaces IP in Altera FPGA Devices</p>