Why is there an unconstrained clock reported when using the Dual Configuration Intel® FPGA IP on Intel® MAX® 10? - Why is there an unconstrained clock reported when using the Dual Configuration Intel® FPGA IP on Intel® MAX® 10? Description An unconstrained clock is reported as shown below when using Dual Configuration Intel® FPGA IP on MAX®10: altera_dual_boot:dual_boot_0|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|ru_clk Resolution To work around this problem, generate timing constraints including the command " create_generated_clock " in the SDC file. Custom Fields values: ['novalue'] Troubleshooting 1506986933 False ['Dual Configuration IP'] ['FPGA Dev Tools Quartus® Prime Software Standard'] novalue 18.1 ['MAX® 10 10 FPGAs'] ['novalue'] ['novalue'] ['novalue']