Why does not the F-Tile HDMI FPGA IP Design Example work for Fixed Rate Link (FRL) 8Gbps? - Why does not the F-Tile HDMI FPGA IP Design Example work for Fixed Rate Link (FRL) 8Gbps? Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.3 and 23.4, TX is unable to complete link training successfully or no image is displayed. This problem is due to the incorrect reconfiguration profiles for Fixed Rate Link (FRL) 8Gbps, resulting in incorrect tx_clkout2 frequency. Resolution There is no workaround for this problem. This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 24.1. Custom Fields values: ['novalue'] Troubleshooting 15014967774 False ['HDMI'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.1 23.3 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']