Why does the O-RAN FPGA IP have a missing IQ sample and asserted error register after processing a valid U-Plane data packet through the receiver transport interface? - Why does the O-RAN FPGA IP have a missing IQ sample and asserted error register after processing a valid U-Plane data packet through the receiver transport interface? Description Due to a problem in the O-RAN FPGA IP version 1.9.1 and earlier, you may see the O-RAN FPGA IP had a missing IQ sample and asserted error register after processing valid U-Plane data packet through the receiver transport interface. Resolution This problem is fixed in the 2.0.0 version of the O-RAN FPGA IP Webcore. Custom Fields values: ['novalue'] Troubleshooting 16020976968 False ['Interfaces'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.3 22.3 ['Agilex™ 7 FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Stratix® 10 DX FPGA', 'Stratix® 10 GX FPGA', 'Stratix® 10 MX FPGA', 'Stratix® 10 NX FPGA', 'Stratix® 10 SX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']