Does the Hard IP for PCI Express for the Avalon-MM interface with DMA support out of order completions? - Does the Hard IP for PCI Express for the Avalon-MM interface with DMA support out of order completions? Description When the Hard IP for PCI Express® read DMA module receives out-of-order completions, the DMA can, in certain instances, flag the descriptor completion signal too early, before all outstanding transactions are completed. Resolution This issue will be fixed in a future version of the Quartus® II software. Custom Fields values: ['novalue'] Troubleshooting novalue False ['DMA'] ['FPGA Dev Tools Quartus II Software'] 14.0 13.1 ['Arria® V GZ FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']