Why can't I read in simulation from the transceiver reconfiguration bus of my Stratix® 10 Low Latency 100 Gbps Ethernet IP core? - Why can't I read in simulation from the transceiver reconfiguration bus of my Stratix® 10 Low Latency 100 Gbps Ethernet IP core? Description Reading the transceiver reconfiguration bus of the Stratix® 10 Low Latency 100 Gbps Ethernet IP is not supported if "Enable ADME" is not checked in the GUI. Resolution In order to read from the transceiver reconfiguration bus of the Stratix® 10 Low Latency 100 Gbps Ethernet IP core in simulation, check the "Enable ADME" dialog box in the IP core GUI. Custom Fields values: ['novalue'] Troubleshooting FB: 579853; HSD: 2205683965 False ['Low Latency 100G Ethernet IP for Arria® 10 and Stratix® V'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 17.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']