How do I remove the on-chip termination from my UniPHY-based memory controller? - How do I remove the on-chip termination from my UniPHY-based memory controller? Description This solution describes the steps to remove the on-chip termination (OCT) from a design that uses UniPHY-based memory controllers. The biggest motivation to remove the OCT from the memory interface I/O is to save power. There are three things to keep in mind: Do not remove the FPGA (on die or on board) termination on any memory I/O operating at least 300 MHz. Do not remove the termination for the mem_clk signal. Perform the signal integrity simulations to check the signal quality after removing the OCT. The steps below describe how to remove the OCT. These steps apply to: DDR3 for Stratix® V, Arria® V and Cyclone® V QDR II for Stratix V and Arria V RLDRAM II for Stratix V Before you start making the modifications to the project, make sure your project has been compiled with no errors. Open the < project_name >.qsf file. Remove or comment out the termination IO assignment in the Quartus® II Settings File (.qsf) or Assignment Editor. For example, comment out the following lines: set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION” To comment out a QSF assignment, add a pound (#) sign at the beginning of the line. For RLDRAM II and QDRII/QDRII only: Remove any QSF constraint starting with set_instance_assignment -name TERMINATION_CONTROL_BLOCK” Start the Quartus compilation. The compilation will fail to fit the design with a bunch of errors. Double click on the first error starting with “Output buffer atom” and it will point to an instantiation of output buffer in altdq_dqs2_stratixv.sv. Remove following connections from that output buffer instantiation. parallelterminationcontrol seriesterminationcontrol dynamicterminationcontrol For example, change .parallelterminationcontrol (parallelterminationcontrol_in), To .parallelterminationcontrol (), Depending upon the memory protocol you are using there might be more than one instances where you need to remove the connections. Repeat step #3 until you get rid of all the errors starting with “Output buffer atom” For DDR2 and DDR3 only: open altdq_dqs2_stratixv.sv. Find the instance named “stratixv_pseudo_diff_out”. Comment out the line where “dtcin” is defined. Change: .dtcin(delayed_oct), To //.dtcin(delayed_oct), Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V FPGAs', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']