Why is there a difference in I/O pin counts for Cyclone® V GX C5 and C7 devices with package F672 in the Cyclone V Device Handbook and Cyclone V Device Pin-Out Files? - Why is there a difference in I/O pin counts for Cyclone® V GX C5 and C7 devices with package F672 in the Cyclone V Device Handbook and Cyclone V Device Pin-Out Files? Description Due to a bug in the Cyclone® V Device Handbook , the number of I/O pin counts are wrongly given in bank 5B and 6A for Cyclone® V GX C5 and C7 devices with package F672. Resolution As a workaround, you can derive the correct number of I/O pins for Cyclone V GX C5 and C7 devices from the respective Cyclone V Device Pin-Out Files . Custom Fields values: ['novalue'] Troubleshooting 1507072578, 1507057291 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 17.0 ['Cyclone® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']