Is the Clock Phase Alignment (CPA) block of the Altera LVDS IP supported for all SERDES factors in Stratix 10 devices? - Is the Clock Phase Alignment (CPA) block of the Altera LVDS IP supported for all SERDES factors in Stratix 10 devices?
Description The Clock Phase Alignment (CPA) block of the Altera® LVDS IP in Intel® Stratix® 10 devices is supported for all SERDES factors from Quartus® Prime Pro version 17.1 onwards under the following conditions: The Use external PLL option is turned off. The IP core functional mode is TX, RX Non-DPA, or RX DPA-FIFO. The tx_outclock phase shift is a multiple of 180°
Custom Fields values:
['novalue']
Troubleshooting
FB: 505476;
False
['LVDS SERDES IP']
['FPGA Dev Tools Quartus® Prime Software Pro']
17.1
17.0
['Stratix® 10 FPGAs and SoCs']
['novalue']
['novalue']
['novalue'] - 2021-08-25
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