Why does the GTS JESD204C IP, F-Tile, and E-Tile JESD204C IP Design Example simulation fail when enabling internal serial loopback in the Design Example tab for the Agilex™ 5, Agilex™ 7, and Stratix® 10 devices? - Why does the GTS JESD204C IP, F-Tile, and E-Tile JESD204C IP Design Example simulation fail when enabling internal serial loopback in the Design Example tab for the Agilex™ 5, Agilex™ 7, and Stratix® 10 devices? Description Due to a problem in the Quartus® Prime Pro Edition Software version 19.2, the GTS JESD204C IP, F-Tile JESD204C IP, and E-Tile JESD204C IP Design Examples do not implement the required register for the transceiver’s internal loopback to be configured. Resolution Internal serial loopback is not supported in the GTS JESD204 IP, F-Tile JESD204C IP, and E-Tile JESD204C IP Design Example. This option will be removed from the Design Example tab starting from the Quartus® Prime Pro Edition Software version 24.3. Custom Fields values: ['novalue'] Troubleshooting 15016661084 False ['JESD204C IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.3 19.2 ['Agilex™ 5 FPGAs and SoCs', 'Agilex™ 7 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']