XIP1213E, Extreme-speed MACSEC AES-GCM IP Core targeting 100G-800G linerates - MACsec is a point-to-point protocol located on layer two (Data Link) of the OSI model. Xiphera designs and implements hardware-based security using proven cryptographic algorithms. Our strong cryptographic expertise and extensive experience in digital system design enable us to help… Arria® 10 SX FPGA Agilex™ 5 FPGA E-Series Arria® V GZ FPGA Agilex™ 9 FPGA Direct RF-Series Agilex™ 7 FPGA I-Series Arria® V SX FPGA Stratix® 10 DX FPGA Stratix® 10 SX FPGA Agilex™ 7 FPGA M-Series Arria® 10 GT FPGA Arria® V ST FPGA Arria® 10 GX FPGA Stratix® 10 TX FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Arria® V GX FPGA Agilex™ 3 FPGA C-Series Stratix® V GS FPGA Stratix® V GX FPGA Agilex™ 5 FPGA D-Series Stratix® 10 GX FPGA Arria® V GT FPGA Agilex™ 7 FPGA F-Series Stratix® 10 AX FPGA Stratix® III FPGA MACsec is a point-to-point protocol located on layer two (Data Link) of the OSI model. Xiphera’s extreme speed MACsec solution safeguards the confidentiality and integrity of data transmitted over point-to-point communication links up to 800G, assured by the Advanced Encryption Standard (AES) in Galois Counter Mode (GCM) with runtime configurable key lengths. Access Aerospace ASIC Proto Broadcast Consumer Data Center Cloud (Public, Private, Hybrid) Defense Government Medical Test Transportation Wireless XIP1213E, Extreme-speed MACSEC AES-GCM IP Core targeting 100G-800G linerates Key Features Moderate resource requirements: The entire XIP1213E requires 218238 Adaptive Lookup Modules (ALMs) (Intel® Agilex® F), and does not require any multipliers or DSPBlocks in a typical FPGA implementation. Offering Brief Yes No No Yes Encrypted Verilog Verilog Arria® 10 SX FPGA Agilex™ 5 FPGA E-Series Arria® V GZ FPGA Agilex™ 9 FPGA Direct RF-Series Agilex™ 7 FPGA I-Series Arria® V SX FPGA Stratix® 10 DX FPGA Stratix® 10 SX FPGA Agilex™ 7 FPGA M-Series Arria® 10 GT FPGA Arria® V ST FPGA Arria® 10 GX FPGA Stratix® 10 TX FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Arria® V GX FPGA Agilex™ 3 FPGA C-Series Stratix® V GS FPGA Stratix® V GX FPGA Agilex™ 5 FPGA D-Series Stratix® 10 GX FPGA Arria® V GT FPGA Agilex™ 7 FPGA F-Series Stratix® 10 AX FPGA Stratix® III FPGA Yes Yes 25.1.1 Offering Brief Production a1JUi0000049USqMAM What's Included Encrypted RTL or source code Ordering Information XIP1213E a1JUi0000049USqMAM Production Intellectual Property (IP) a1MUi00000BO8toMAD a1MUi00000BO8toMAD Select 2026-04-21T12:58:33.000+0000 MACsec is a point-to-point protocol located on layer two (Data Link) of the OSI model. Partner Solutions