Some Designs with User Partitions and State Machines Might Encounter Fatal Errors during Analysis and Synthesis - Some Designs with User Partitions and State Machines Might Encounter Fatal Errors during Analysis and Synthesis
Description In the Quartus ® II software and the Quartus Prime Standard Edition software, some designs that include user partitions and state machines might encounter fatal errors during the Analysis and Synthesis stage of the compilation flow. Resolution Disable parallel synthesis by adding the following Quartus Prime Settings File (QSF) setting: set_global_assignment -name PARALLEL_SYNTHESIS OFF
Custom Fields values:
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Troubleshooting
FB370057;
True
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['FPGA Dev Tools Quartus® Prime Software Standard']
16.0.1
15.0
['Programmable Logic Devices']
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['novalue'] - 2021-08-25
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