Why do I get an error in Platform Designer during the Generate HDL process for systems which include the DDR3 SDRAM Controller with UniPHY Intel® FPGA IP core - Why do I get an error in Platform Designer during the Generate HDL process for systems which include the DDR3 SDRAM Controller with UniPHY Intel® FPGA IP core Description Due to a problem in the Intel® Quartus® Prime Standard Edition Software version 21.1, you may not be able to Generate HDL for your Platform Designer system in the Windows operating system (OS). The problem may occur if your system includes the DDR3 SDRAM Controller with UniPHY Intel® FPGA IP core. Error: border: Error during execution of script generate_hps_sdram.tcl: seq: Error during execution of "{C:/intelfpga/21.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally Resolution To work around this problem, download and install the following patch according to the versions of your Intel® Quartus® Prime Standard Edition Software: Intel® Quartus® Prime Standard Edition Software v21.1 Solution Patch 0.01 for Windows (.exe) Intel® Quartus® Prime Standard Edition Software v21.1 Solution Patch 0.01 for Linux (.run) Readme for Intel® Quartus® Prime Standard Edition Software v21.1 Solution Patch 0.01 (.txt) This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Standard Edition Software. Custom Fields values: ['novalue'] Troubleshooting 16015124034 True ['Memory Interfaces and Controllers'] ['FPGA Dev Tools Quartus® Prime Software Standard'] 21.2 21.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']