SystemVerilog with Quartus® Prime Design Software - 18 Minutes SystemVerilog is a hardware description and verification language that is widely used in the electronic design automation (EDA) industry. It is a powerful and versatile language that combines the capabilities of hardware description languages (HDLs) such as VHDL and Verilog with the features of programming languages such as C and C++. SystemVerilog is used to design, verify, and document electronic systems, including digital, analog, and mixed-signal systems. It is particularly useful for modeling complex digital logic and for verifying the correctness of hardware designs through simulation and formal verification. This training focuses on the SystemVerilog features for RTL design. Course Objectives At course completion, you will be able to: Implement SystemVerilog data types and declarations Implement SystemVerilog procedural blocks Implement procedural statements including SystemVerilog-enhanced case statements Implement state machines using SystemVerilog coding styles Take advantage of the enhanced port connections in SystemVerilog Skills Required Background in digital logic design Basic knowledge of Verilog HDL Familiarity with the Quartus® Prime software If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OHDL1125. FPGA_OHDL1125. <p>SystemVerilog with Quartus Prime Design Software</p>