Why does programming the csr_cgs_bypass_sysref register bit to '0' when the JESD204B Intel® FPGA IP is in ILAS phase bring the IP back to CGS state? - Why does programming the csr_cgs_bypass_sysref register bit to '0' when the JESD204B Intel® FPGA IP is in ILAS phase bring the IP back to CGS state? Description Due to a known problem in the Intel® Quartus® Prime Standard and Pro Edition Software, programming the csr_cgs_bypass_sysref register bit to ' 0 ' when the JESD204B Intel FPGA IP is in ILAS phase will bring the IP back to CGS state. This impacts Intel Agilex®, Intel Stratix® 10, Intel Arria® 10 and Intel Cyclone® 10 GX device families. Resolution To work around this problem, avoid programming the csr_cgs_bypass_sysref register bit when the JESD204B Intel FPGA IP is in ILAS phase. There is no fix planned for this. Custom Fields values: ['novalue'] Troubleshooting 1507197255 False ['JESD204B IP'] ['FPGA Dev Tools Quartus® Prime Software Pro', 'FPGA Dev Tools Quartus® Prime Software Standard'] novalue 18.1 ['Agilex™ 7 FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']