Why do I see an efficiency issue when using the Arria® V and Cyclone® V hard memory controller with DQS tracking enabled? - Why do I see an efficiency issue when using the Arria® V and Cyclone® V hard memory controller with DQS tracking enabled? Description Arria® V and Cyclone® V DDR2, DDR3/3L, and/or LPDDR2 designs with DQS tracking enabled may see reduced efficiency due to a long DQS tracking process where there is no periodic refresh being issued by the hard memory controller for a long period of time. Resolution Enable user auto-refresh options in the UniPHY IP. Custom Fields values: ['novalue'] Troubleshooting 2205870273 False ['DDR2 SDRAM Controller with UniPHY IP', 'DDR3 SDRAM Controller with UniPHY IP', 'LPDDR2 SDRAM Controller with UniPHY IP'] ['FPGA Dev Tools Quartus® Prime Software QUARTUS-ALITE', 'FPGA Dev Tools Quartus® Prime Software Standard'] novalue 14.1.1 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']