Why can't the E-Tile perform dynamic reconfiguration from a low data rate to a high data rate, when the design starts at a low data rate? - Why can't the E-Tile perform dynamic reconfiguration from a low data rate to a high data rate, when the design starts at a low data rate? Description Due to a problem with the E-Tile Transceiver Native PHY IP, dynamic reconfiguration from a low data rate to a high data rate fails, when the design is started at a low data rate. For example, it does not allow dynamic reconfiguration from 2.4576 Gbps PMA-direct (20-bit, 122.88 MHz transfer speed) to the higher data rate of 24.33024 Gbps with PCS and FEC (32-bit, 760.32 MHz transfer speed). Resolution For the Intel® Quartus® Prime Pro Edition Software version 20.4 and earlier, designs need to start at a high rate first and then dynamically reconfigure to any rate. This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.2. Custom Fields values: ['novalue'] Troubleshooting 14010478744, 18015710881 False ['Transceiver PHY'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.2 19.3 ['Agilex™ 7 FPGA F-Series', 'Stratix® 10 DX FPGA', 'Stratix® 10 MX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']