Why am I unable to program the EPCQ-L configuration device with a .jic file on an Intel® Arria® 10 SoC Development Kit? - Why am I unable to program the EPCQ-L configuration device with a .jic file on an Intel® Arria® 10 SoC Development Kit? Description You might see the following error message in the Intel® Quartus® Prime Software Programmer when programming the EPCQ-L configuration device with a .jic file on a Revision B Intel® Arria® 10 SoC Development Kit. Error (209012) : Operation Failed. CONF_DONE failed to go high By default, the JTAG chain on the development kit consists of an Intel Arria 10 FPGA, its HPS and a MAX® V device (the I/O MUX CPLD). In addition to this, the TCK frequency of the on-board Intel® FPGA Download Cable II defaults to 24 MHz Since the minimum JTAG TCK period for MAX V devices is 100 ns, it is the slower device in the JTAG chain and contributes towards the configuration failure. Resolution To program the EPCQ-L device on the Intel Arria 10 SoC Development Kit successfully with a .jic file, follow either of these two steps: While programming with the default board settings, (Intel Arria 10 and MAX V devices enabled in the JTAG chain) reduce the JTAG clock to 6 MHz with the command : "jtagconfig --setparam <cable name> JtagClock 6M" Remove the MAX V CPLD from the chain by setting the 3rd bit of DIP SW3 to the OFF position. Custom Fields values: ['novalue'] Troubleshooting FB: 405821;2205831242 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue No plan to fix ['Arria® 10 FPGAs and SoCs', 'MAX® V CPLDs'] ['Stand-Alone Programmer 10.23 (For Legacy Max+Plus® II Software)'] ['novalue'] ['novalue']