Why is the input port signal of IP instance is not inverted in Signal Tap after an upper-level port signal is directly inverted on the instance port? - Why is the input port signal of IP instance is not inverted in Signal Tap after an upper-level port signal is directly inverted on the instance port? Description In the Quartus® Prime Pro Edition Software, if you invert the upper-layer port signal to the port of an FPGA IP instance as follows: module top ( input clk, input reset, ... ); nco inst ( .clk (clk), .reset_n (~reset) ... ); ... endmodule You may see that the signal on the IP port captured by the Signal Tap remains the same as the upper-layer port signal; no signal inversion occurred. The instance's output will work as expected after the upper-layer reset is deasserted. Resolution This is because the synthesis stage has merged the invert inside the FPGA IP with the invert outside the FPGA IP, and both have been optimized. Custom Fields values: ['novalue'] Troubleshooting 15016105956 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 24.1 ['Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']