Why does the GTS SDI II IP Multi-rate Dual Simplex Serial Loopback Design Example fail to achieve lock on Agilex™ 5 FPGA E-Series Premium Development Kit at 12G data rate? - Why does the GTS SDI II IP Multi-rate Dual Simplex Serial Loopback Design Example fail to achieve lock on Agilex™ 5 FPGA E-Series Premium Development Kit at 12G data rate? Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3, you may observe the rx_align , rx_frame and rx_trs signals fail to achieve lock when running the GTS SDI II IP Multi-rate Serial Loopback Design Example on Agilex™ 5 FPGA E-Series Modular Development Kit at 12G data rate. Resolution There is no workaround. This problem will be fixed in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15018542969 novalue ['Interfaces Audio/Video SDI II (Primary)'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 25.3 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']