Why is the pll_powerdown port of the Intel® Stratix® V device Transceiver Native PHY IP Core not removed when I enable the Use external TX PLL option? - Why is the pll_powerdown port of the Intel® Stratix® V device Transceiver Native PHY IP Core not removed when I enable the Use external TX PLL option? Description Due to a problem in the Quartus® II software, the pll_powerdown port of the Stratix® V device Transceiver Native PHY IP Core is not removed when the “Use external TX PLL” option is enabled. This pll_powerdown port is not connected to any submodule, and you can connect it to '0' in your design. Resolution This pll_powerdown port is not connected to any submodule, and you can connect it to '0' in your design. Custom Fields values: ['novalue'] Troubleshooting 2205826859 False ['PLL IP'] ['FPGA Dev Tools Quartus II Software'] No plan to fix 12.1.1 ['Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']