Error (suppressible): (vsim-3058) The width (83) of Verilog port 'av_st_din_data' does not match the array length (48) of its VHDL connection - Error (suppressible): (vsim-3058) The width (83) of Verilog port 'av_st_din_data' does not match the array length (48) of its VHDL connection Description Due to a problem in the Quartus® Prime software version 17.0 update 1 and earlier, you may see the error mentioned above while running VHDL VHDL-based simulation model for the Clock Video Output II IP core. Resolution This issue has no workaround; the user must install the Quartus® Prime Pro Edition Software version 20.2 to resolve it. Custom Fields values: ['novalue'] Troubleshooting 474035 507520 475719 507548 False ['Clocked Video Output II (4K Ready) IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.2 17.0.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']