Why do I see timing violations in the Stratix V and Arria V GZ device Reconfiguration Controller IP when the Bit Error Rate block is enabled? - Why do I see timing violations in the Stratix V and Arria V GZ device Reconfiguration Controller IP when the Bit Error Rate block is enabled? Description Due to the "set_max_skew" constraint contained in the reconfiguration controller's alt_xcvr_reconfig.sdc file, you might see timing violations in the Stratix® V and Arria® V GZ device Reconfiguration Controller IP when the Bit Error Rate Block is enabled. Resolution To help close timing, the "set_max_skew" constraint can be removed from the alt_xcvr_reconfig.sdc file. This will reduce congestion and routing effort due to the Bit Error Rate accumulators. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 13.1 ['Arria® V GZ FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']