XIP1213B: MACSEC AES256-GCM IP core targeting 1Gbps+ links - MACsec is a point-to-point protocol located on layer two (Data Link) of the OSI model. Xiphera designs and implements hardware-based security using proven cryptographic algorithms. Our strong cryptographic expertise and extensive experience in digital system design enable us to help… Intel® Arria® 10 SX SoC FPGA Cyclone® IV GX FPGA Intel Agilex® 5 FPGAs and SoC FPGAs E-Series Intel® MAX® 10 FPGA Cyclone® V SX SoC FPGA Arria® V GZ FPGA Intel Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series MAX® V CPLD Intel Agilex® 7 FPGAs and SoC FPGAs I-Series Arria® V SX SoC FPGA Intel® Stratix® 10 DX FPGA Intel® Stratix® 10 SX SoC FPGA Intel Agilex® 7 FPGAs and SoC FPGAs M-Series Cyclone® V GT FPGA Intel® Arria® 10 GT FPGA Arria® V ST SoC FPGA Intel® Arria® 10 GX FPGA Intel® Stratix® 10 TX FPGA Cyclone® V SE SoC FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Arria® V GX FPGA Cyclone® V E FPGA Intel Agilex® 3 FPGAs and SoC FPGAs C-Series Cyclone® V GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Cyclone® V ST SoC FPGA Intel Agilex® 5 FPGAs and SoC FPGAs D-Series Intel® Stratix® 10 GX FPGA Arria® V GT FPGA Intel® Cyclone® 10 LP FPGA Intel Agilex® 7 FPGAs and SoC FPGAs F-Series Intel® Cyclone® 10 GX FPGA Intel® Stratix® 10 AX SoC FPGA Cyclone® IV E FPGA Stratix® III FPGA MACsec is a point-to-point protocol located on layer two (Data Link) of the OSI model. Xiphera’s comprehensive MACsec solution portfolio safeguards the confidentiality and integrity of data transmitted over point-to-point communication links, assured by the Advanced Encryption Standard (AES) in Galois Counter Mode (GCM) with 256-bit key length. Access Aerospace ASIC Proto Broadcast Consumer Data Center Cloud (Public, Private, Hybrid) Defense Government Medical Test Transportation Wireless XIP1213B: MACSEC AES256-GCM IP core targeting 1Gbps+ links Key Features Moderate resource requirements: The entire XIP1213B requires 9907 Adaptive Lookup Modules (ALMs) (Altera® Cyclone® 10 GX), and does not require any multipliers or DSPBlocks in a typical FPGA implementation. Offering Brief Yes No No Yes Encrypted VHDL VHDL Intel® Arria® 10 SX SoC FPGA Cyclone® IV GX FPGA Intel Agilex® 5 FPGAs and SoC FPGAs E-Series Intel® MAX® 10 FPGA Cyclone® V SX SoC FPGA Arria® V GZ FPGA Intel Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series MAX® V CPLD Intel Agilex® 7 FPGAs and SoC FPGAs I-Series Arria® V SX SoC FPGA Intel® Stratix® 10 DX FPGA Intel® Stratix® 10 SX SoC FPGA Intel Agilex® 7 FPGAs and SoC FPGAs M-Series Cyclone® V GT FPGA Intel® Arria® 10 GT FPGA Arria® V ST SoC FPGA Intel® Arria® 10 GX FPGA Intel® Stratix® 10 TX FPGA Cyclone® V SE SoC FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Arria® V GX FPGA Cyclone® V E FPGA Intel Agilex® 3 FPGAs and SoC FPGAs C-Series Cyclone® V GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Cyclone® V ST SoC FPGA Intel Agilex® 5 FPGAs and SoC FPGAs D-Series Intel® Stratix® 10 GX FPGA Arria® V GT FPGA Intel® Cyclone® 10 LP FPGA Intel Agilex® 7 FPGAs and SoC FPGAs F-Series Intel® Cyclone® 10 GX FPGA Intel® Stratix® 10 AX SoC FPGA Cyclone® IV E FPGA Stratix® III FPGA Yes Yes 25.1.1 Offering Brief Production a1JUi0000049USoMAM What's Included Encrypted RTL or source code Ordering Information XIP1213B a1JUi0000049USoMAM Production Intellectual Property (IP) a1MUi00000BO8toMAD a1MUi00000BO8toMAD Select 2025-09-28T23:54:20.000+0000 MACsec is a point-to-point protocol located on layer two (Data Link) of the OSI model. Partner Solutions